1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to an integrated circuit (IC) device that includes DMOS and other semiconductor devices in a common wafer and to methods of fabricating the same.
2. Description of the Related Art and Summary of the Invention
MOSgated devices remain prevalently used semiconductor devices. As used herein, generally, a MOSgated device refers to a MOSFET, IGBT or the like. Devices comprising integrated circuits typically use MOSgated devices, for example, for power switching and transfer. It is desirable to have an IC which includes DMOS devices along with other devices.
An integrated circuit according to the present invention includes a semiconductor wafer. The wafer includes a plurality of electrically isolated semiconductor devices.
According to one aspect of the present invention, at least one of the devices is a vertical conduction DMOS that includes a gate, one power electrode on one side thereof, and another power electrode on an opposing side thereof. In the preferred embodiment, the DMOS is a MOSFET. According to an aspect of the present invention the DMOS is disposed in an insulation tub, which is formed by trenched insulation walls that intersect a buried insulation layer. In the preferred embodiment, each of the semiconductor devices is disposed in a respective insulation tub.
According to another aspect of the present invention, the wafer includes a first wafer that is bonded to a second wafer. Preferably, the two wafers are bonded through an insulation layer, such as a silicon dioxide layer, which then serves as the buried insulation layer. An example of such a wafer is conventionally referred to as a silicon on insulator (SOI) wafer. It should be noted techniques other than bonding may be used to obtain an SOI wafer without deviating from the scope and spirit of the present invention.
In a method according to the present invention, a plurality of trenches are formed in the first semiconductor wafer of an SOI wafer, each trench reaching at least the buried insulation body. Thereafter, the trenches are filled with an insulation body to form insulation walls, whereby insulation walls and the buried insulation body form insulation tubs each around a semiconductor body.
According to one aspect of the present invention, each of the plurality of semiconductor devices is formed in the first wafer prior to forming the trenches, whereby the trenches are used to isolate the semiconductor devices from one another prior to filling the trenches with an insulation body.
According to another aspect of the present invention, a vertical conduction DMOS is formed in at least one of the semiconductor bodies, a portion of the second wafer (which may be made from silicon) and a portion of the buried insulation body are removed from under the DMOS, and a second power electrode is formed to make contact with the back of the DMOS to obtain a vertical conduction DMOS in the single wafer.